Digital sawtooth generator

ABSTRACT

A digital sawtooth waveform generator is disclosed for providing a motor reference signal in a cycloconverter power supply for an induction motor. A series of clock pulses at a frequency J(Fsync) is supplied to the clock input of a binary counter where J is a constant and Fsync is the desired frequency of the input signal to the motor. Preset pulses at a frequency of 2Fsync are supplied to the binary counter whose output is applied to a variable gain digital-to-analog converter. A gain control voltage with a magnitude of VG is applied to the digital-to-analog converter whose output is a current I1 with a magnitude equal to VGK1N where K1 is a constant and N is the count of the binary counter. The current I1 is summed with a current I2 having a magnitude equal to K3VG, where K3 is a constant and where the currents I1 and I2 have opposite polarities, and a biasing current I3. The summed currents form the sawtooth waveform at the frequency 2Fsync. The current I2 establishes a point on the sawtooth waveform about which it is compressed or expanded as the magnitude VG of the gain control voltage is varied and which is independent of the magnitude of the biasing current I3.

United States Patent 1 1 Matouka 1 1 Dec.2, 1975 1 1 DIGITAL SAWTOOTHGENERATOR Michael F. Matouka, Sterling Heights, Mich.

[75] Inventor:

[22] Filed: Apr. 8, 1974 [2]] Appl. No.: 458,562

[52] US. Cl. 328/181; 318/227; 328/35; 328/185; 328/186 151] Int. ClH03k 4/10; H0314 3/37 [58] Field of Search 307/227. 228; 318/227;328/35, 181-186 [56] References Cited UNITED STATES PATENTS 2.958.82811/1960 Schreiber 328/186 3,628,061 12/1971 .lackman... 328/1863.676.784 7/1972 Comte 328/181 3,835.4(13 9/1974 Leinemann 328/186Primary Examiner Stanley D. Miller, Jr. Attorney. Agent, or FirmHowardN. Conkey PRESET A PRESET B R; REFERENCE GENERATOR CLK-B PRESET C R:REFERENCE CLK C GENERATOR GAIN CONTROL VOLTAGE 1571 ABSTRACT A digitalsawtooth waveform generator is disclosed for providing a motor referencesignal in a cycloconverter power supply for an induction motor. A seriesof clock pulses at a frequency J(F is supplied to the clock input of abinary counter where .1 is a constant and P is the desired frequency ofthe input signal to the motor. Preset pulses at a frequency of 2F aresupplied to the binary counter whose output is applied to a variablegain digital-to-analog converter. A gain control voltage with amagnitude of V is applied to the digital-to-analog converter whoseoutput is a current 1 with a magnitude equal to V ,-K,N where K is aconstant and N is the count of the binary counter. The current 1 issummed with a current 1 having a magnitude equal to Kgvn, where K, is aconstant and where the currents l1 and 1 have opposite polarities, and abiasing current 1 The summed currents form the sawtooth waveforn iat thefrequency ZF The current 1 establishes a point on the sawtooth waveformabout which it is compressed or expanded as the magnitude V of the gaincontrol voltage is varied and which is independent of the magnitude ofthe biasing current 1 3-Claims, 11 Drawing Figures Dec. 2, 1975 Sheet 1of 7 3,924,195

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US. Patent Dec. 2, 1975 Sheet 2 of7 3,924,195

US. Patent Dec. 2, 1975 Sheet 3 of7 3,924,195

FF8Q FFZQ US. Patent Dec. 2, 1975 Sheet 4 of 7 r r V I, r '7 DIGITALSAWTOOTII GENERATOR This invention relates to a digital sawtoothwaveform generator. Digital sawtooth waveform generators are generallyknown and usually take the form of a clock pulse generator, a counterand a digital-to-analog converter whose output comprises the sawtoothwaveform. These known systems are generally unacceptable for use inapplications such as representing the desired firing angle of controlledrectifiers in a cycloconverter circuit because of their lack ofversatility and particularly in their inability to readily modify thesawtooth waveform characteristics during operation. For example, inknown generators, it is not possible to vary the peak-to-peak amplitudeof the sawtooth waveform to vary the firing angle range of thecontrolled switches and yet maintain the controlled switch firing anglerepresentation at a specific angle of the sawtooth waveform a constant.

It is the general object of this invention to provide an improveddigital sawtooth waveform generator.

It is another object of this invention to provide a digital sawtoothwaveform generator for generating a sawtooth waveform which may becompressed or expanded about a preselected point on the sawtoothwaveform.

It is another object of this invention to provide for a digital sawtoothwaveform generator wherein the sawtooth waveform may be compressed orexpanded about a preselected angle of the sawtooth waveform for allpeak-to-peak amplitudes and frequencies thereof.

The digital sawtooth waveform generator of this invention includes acounter to which a series of clock pulses are applied at a frequency JFwhere J is a constant and F is the desired output frequency. The counteris set by preset pulses at a frequency equal to F such that the outputof the counter is the binary indication of the contents of the counterbetween preset pulses. The output of the counter is applied to avariable gain digital-to-analog converter. A gain control voltage isgenerated having a magnitude V and is applied to the digital-to-analogconverter whose output is a current I having a magnitude equal to V K Nwhere K is a constant and N is the count of the binary counter. Thiscurrent is a stepped waveform with the magnitude of the steppedincrements and the peak-topeak amplitude being controlled as a functionof the gain control voltage. The current I is summed with a bias currentI and a current I having a magnitude equal to K V where K is a constantand where the currents I and I have opposite polarities. The summedcurrent is the sawtooth Waveform at the frequency F. The current Iestablishes a point on, or angle of, the sawtooth waveform about whichit is compressed or expanded as the magnitude V of the gain controlvoltage is varied. The amplitude of the sawtooth waveform at this angleis controlled by the magnitude of the current I3.

The objects of this invention may be best understood by reference to thefollowing description of a preferred embodiment of this inventionincorporated in a cycloconverter power supply and the Figures in which:

FIG. 1 is a system diagram of an induction motor power and brakingsystem wherein the motor reference generator comprises the sawtoothwaveform generator of this invention.

FIG. 2 is a diagram illustrating various voltage waveforms and theirtimed relationship as developed by the system of FIG. 1.

FIG. 3 is a circuit diagram of the trigger logic circuit associated withone of the phases of the cycloconverter output.

FIG. 4 is a diagram illustrating the voltage waveforms and their timedrelationship developed by the logic system of FIG. 3.

FIG. 5 is a circuit diagram of the input circuit of the motor referencegenerator of FIG. 1 for generating clocking signals for the phase A, Band C counters.

FIG. 6 is a logic circuit in the motor reference generator of FIG. 1 forgenerating preset signals for the phase A, B and C counters.

FIG. 7 is a circuit diagram of the output circuit of the motor referencegenerator of FIG. 1 showing the phase A, B and C counters anddigital-to-analog converters.

FIGS. 8a and 8b are diagrams illustrating the logic signals and themotor reference signal which are generated by the circuits of FIGS. 5, 6and 7 during motoring and braking; and

FIGS. 9a and 9b are diagrams illustrating control of the motor referencewaveform by the motor reference generator of FIG. 1.

Referring to the drawings and more particularly to FIG. 1, there isillustrated an electric propulsion system for a vehicle which includes asource of polyphase alternating current generally designated byreference numeral 10. This source of alternating current is a threephaseY-connected generator having an output winding 12 and a field winding14. The field winding 14 is serially connected with a source of directcurrent 16 through a variable resistor 18. The variable resistor 18provides for regulation of the current through the field winding 14 tothereby regulate the output voltage of the output winding 12. It isunderstood that the variable resistor 18 merely illustrates variousfield current control devices which could take a variety of forms suchas a transistor voltage regulator.

The system to be described may be used for the electric propulsion of avehicle such as an earthmover in which case the field winding 14 wouldbe carried by the generator rotor (not illustrated) and driven by aprime mover such as a turbine or diesel (not illustrated). It isunderstood that the source of alternating current could be a three-phasecommercial power source if the present invention were incorporated in amotor control system in a manufacturing facility.

The output of the winding 12 comprises a threephase line-to-neutralvoltage having phases x, y and z, as illustrated in FIG. 2, appliedrespectively to output conductors 20, 22 and 24. The frequency andamplitude of this three-phase voltage is determined by the operatingconditions of the alternating current source 10. For purposes of thefollowing discussion, the frequency and magnitude of the phase voltagex, y and z are assumed to be constant.

In the earthmover application, a three-phase induction motor 28 is usedhaving phase windings 30-A, 30-B and 30-C to which a three-phase voltagehaving phases A, B and C is applied to provide drive power for vehiclepropulsion. The induction motor 28 includes a rotor 32 which is coupledto a vehicle wheel 34 to drive the vehicle. The coupling between therotor 32 and the wheel 34 may include a mechanical differential or othercoupling means. In addition, it is understood that each wheel may bedriven by a separate motor or a plurality Cl+ through C6+ and Cl throughC6 respectively and each being connected in a full wave bridge rectifierconfiguration with the conductors 20, 22 and 24 being connected torespective inputs of each bridge.

' The outputs of the two groups of controlled rectifiers A+ and A- areconnected to the phase winding 30A of the induction motor 28 viaconductors 36 and 38. The set of controlled rectifiers Al+, A2+ and A3+are poled to supply current to the phase winding 30A via the conductor36, the set of controlled rectifiers A4+,

A+ and A6+ are poled to return current from the phase winding -A to thewindingl2 via the conductor 38, the set of controlled-rectifiers Al, A2and A3 are poled to return current from the phase winding 30-A to thewinding 12 via the conductor 36 and the set of controlled rectifiers A4,A5 and A6- are poled to supply current to the phase winding 30-A via theconductor 38. By controlling the firing angles of the controlledrectifiers in the A+ and A groups relative to the line-to-line voltagesfrom the winding 12, as will be described, the phase A voltage isgenerated and sup plied to the phase winding 30-A.

In like manner, the outputs of the two groups of controlled rectifiersB+ and B are connected to the phase winding 30-B via the conductors 40and 42 and the outputs of the two groups of controlled rectifiers Cl andC' are connected to the phase winding 30-C via the conductors 44 and 46.

' A braking grid resistor 48 is series connected with a contactor 50across the conductors 36 and 38, a braking grid resistor 52 is seriesconnected with a contactor 54 across the conductors 40 and 42 and abraking grid resistor 56 is series connected with a contactor 58 acrossthe conductors 44 and 46. When it is desired to operate the inductionmotor 28 for motoring, the contactors 50, 54 and 58 are opened.Conversely, when it is desired to operate the induction motor 28 as abrake, the contactors 50, 54 and 58 are closed to connect the brakinggrid resistors 48, 52 and 56 in parallel with the respective phasewinding 30-A, 30-B and 30-C.

To provide for motoring or braking, the six groups of controlledrectifiers A+, B, B+, B, C+ and C- are controlled so as to apply thethree-phase voltage having for generating a series of voltage pulseshaving a frequency J (F,,,), where .l is a constant and F divided by thenumber of motor pole pairs is the rotational speed of the rotor 32. Thetachometer 60 can take a variety of known forms including a toothedwheel and a pickup coil.

The output voltage pulses from the tachometer 60 are supplied to theslip frequency controller 62 which, under the control of the motoringand braking control 64 generates a series of voltage pulses having afre- 4 quency J(F,.,,,, where P F F and F is the desired slip frequencyof the induction motor 28. When the induction motor 28 is used formotoring, the slip frequency F is positive and when the induction motor28 is being operated as a brake, the slip frequency F is a negativevalue. The motoring and braking control 64 controls the slip frequencycontroller 62 to provide for the positive or negative slip as a functionof vehicle operator demand. In addition, the motoring and brakingcontrol 64 functions in response to operator demand during braking toclose the contactors 50, 54 and 58. The aforementioned functions of theslip frequency controller 62 and the motoring and braking control 64 maybe accomplished as illustrated in the US. Pat. Salihi et al. No.3,688,171 which issued on Aug. 29, 1972 and which is assigned to theassignee of this invention. The motoring and braking control 64 furtherfunctions in response to operator demand to supply a logic 1 signal formotoring and a logic 0 signal for braking on an output line 63 and tosupply a gain control signal having a magnitude V representing a desiredbraking or motoring demand on an output line 65.

The voltage pulses from the slip frequency controller 62 at thefrequency J(F is supplied to a group control generator 66 and a motorreference generator 68 comprising the sawtooth waveform generator ofthis invention.

The group control generator 66 is responsive to the voltagepulsessupplied thereto for generating three group signals GP GP 3 and GP asillustrated in FIG. 2,

I each of which is a square wave at the desired frequency F ==F F andfurther which are displaced from one another. The group controlgenerator 66 may take the form of counters and appropriate logicelements to generate the three group signals GP GP B and GP The groupsignal GP is further supplied to the motor reference generator 68 tosynchronize the operation of the motor reference generator 68 with thegroup signals GP GP,; and GP The motor reference generator 68 generatesthree motor reference signals R R and R each having a period equal to ofthe desired input voltage to the. induction motor 28 and consequentlyequal to 180 of the group reference signals GP GP and GP and each havinga fast falling trailing edge at the beginning of each period. Each ofthe motor reference signals R R3 and R takes the form of a series ofsawtooth waveforms of the conventional type during braking or of thetruncated type during motoring. For purposes of illustration, it willhereinafter be assumed that the induction motor 28 is being operated asa brake so that the motor reference signals R R and R are sawtoothwaveforms of the conventional type as illustrated in FIG. 2.

The instantaneous amplitude of each of the motor reference signals R,,,R B and R represents the desired firing delay angle of controlledrectifiers in the respective group pairs A+ and A, 8+ and B, C+ and C.The group signal GP supplied to the motor reference generator 68functions to synchronize the motor reference signals R R B and R withthe group signals GP GP 8 and GP respectively, as seen in FIG. 2, sothat the period of each motor reference signal R,,, R and Rsubstantially coincides with each 180 segment of the respective groupreference signal GP GP and GP As seen in FIG. 2, the motor referencesignals R,,, R and R are digitally synthesized sawtooth waveforms eachhaving a fast falling trailing edge occurring within a short time periodfollowing each 180 segment of the corresponding group signal GP GP,, orOF The fast falling trailing edge of the motor reference signals R,,, Rand R make possible the smooth transition of load current between eachof the pairs of controlled rectifier groups associated with each phasewinding of the induction motor 28.

Conductors and 24 connect phase voltages x and z to respective inputs ofa comparator 70, conductors 20 and 22 connect phase voltages x and y torespective inputs of a comparator 72 and conductors 22 and 24 connectphase voltages y and z to respective inputs of a comparator 74. Thecomparators 70, 72 and 74 generate respective square wave signals X, Yand Z illustrated in FIG. 2 which are in synchronism with the zerovoltage crossings between the conductors 20 and 24, 20 and 22, and 22and 24 respectively. Each state of the square wave signals X, Y and Zrepresents the firing angle range of a respective controlled rectifierin each of the groups A+, A, B+, B, C+ and C. The square wave signals X,Y and Z are connected to respective pulse generators 76, 78 and 80. Thepulse generators 76, 78 and 80 are responsive to the square wave signalsX, Y and Z for producing a positive voltage pulse upon each leading andtrailing edge of the respective square wave signals X. Y and Z. Thepulse output of the pulse generators 76, 78, and 80 are connected torespective source reference generators 82, 84 and 86.

The source reference generators 82, 84 and 86 are responsive to thepulse inputs thereto for generating three-phase source reference signalsR Ry and R comprised of series of sawtooth waveforms of the conventionaltype which are in synchronism with zero lineto-line voltage crossoversof the voltages between the conductors 20 and 24, 20 and 22, and 22 and24 respectively as seen in FIG. 2. These sawtooth source referencesignals R Ry and R have a constant peak amplitude at all frequencies ofthe output of the source of alternating current 10. The instantaneousmagnitude of each of the sawtooth waveforms in the source referencesignals R Ry and R is proportional to the firing delay angle ofrespective controlled rectifiers in the controlled rectifier groups A+,A, B+, B-, C+ and C. The source reference generators 82, 84 and 86 eachmay take the form of the sawtooth generator described in the US. Pat.Salihi et al. No. 3,659,168 which issued on Apr. 25, 1972 and which isassigned to the assignee of the present invention.

The motor reference signal R is compared with each of the sourcereference signals R Ry and R in comparators 88, 90 and 92 respectively.The resulting logic signals V V, and V are illustrated in FIG. 4 and arein synchronism with the desired firing angles of the controlledrectifiers in the groups A+ and A-. The motor reference signal R,, iscompared with each of the source reference signals R Ry and R incomparators 94, 96 and 98 respectively. The resulting logic signals V Vand V are in synchronism with the desired firing angles of thecontrolled rectifiers in the groups B+ and B. The motor reference signalR is compared with the source reference signals R Ry and R incomparators 100, 102 and 104 respectively to generate logic signals V Vand V which are in synchronism with the desired firing angles of thecontrolled rectifiers in the groups C+ and C.

The outputs of the comparators 88, 90 and 92 are supplied to a phase Atrigger logic circuit 106, the outputs of the comparators 94, 96 and 98are supplied to a phase B trigger logic circuit 108 and the outputs ofthe comparators 100, 102 and 104 are supplied to a phase C trigger logiccircuit 110. The square wave signals X, Y and Z are each connected tothe phase A, Band C trigger logics 106, 108 and 110. The group signal GPis connected to the phase A trigger logic 106, the group signal GP isconnected to the phase B trigger logic 108 and the group signal GP isconnected to the phase C trigger logic 110.

The phase A trigger logic 106 processes the input signals thereto toobtain the trigger signals for the controlled rectifiers in the groupsA+ and A- to generate the phase A alternating voltage applied to thephase winding 30-A of the induction motor 28. In like manner, the phaseB trigger logic 108 and phase C trigger logic 110 process the respectivesignal inputs thereto and generate the tripper signals for thecontrolled rectifiers in the groups B+ and B and C+ and C respectivelyto generate the phase B and C alternating voltages applied to the phasewindings 30-3 and 30-C respectively. The 'periods of the phase A, B andC currents coincide respectively with the group signals GP GP and GP andas such are phase displaced from one another.

Referring to FIGS. 3 and 4, the phase A trigger logic circuit 106:includes a plurality of flip-flops FFI through FF12. Each of theflip-flops includes a two input AND gate controlled set input, a clockinput, a single input AND gate controlled reset input, a direct resetinput, a Q output and a Q output. The flip-flops FFl through FF12 are ofthe well-known type wherein the Q output is set to a logic 1 when theclock input changes from a logic 1 to a logic 0 while the set input is alogic 1. These flip-flops are also reset when the clock input changesfrom a logic 1 to a logic 0 while the reset input is a logic 1. Further,an input to the direct reset input changing from a logic 1 to a logic 0resets the flip-flop.

The flip-flops FFl through FF6 are enabled by the group signal GP whichis supplied to one input of the AND gate at the respective set inputsand the inverse of which-is applied to the AND gate input of therespective reset inputs. While the group signal GP is a logic 1, theflip-flops FFl through FF6 are each set when the remaining input to theAND gate coupled to the set input of the flip-flops is a logic 1 and theclock input thereof changes from a logic 1 to a logic 0.

The signals X, Y and Z are supplied respectively to the remaining inputsof the AND gates at the set inputs of the flip-flops FFl through FF3.The logic signals V V and V are supplied to the respectiye clock inputsof the flip-flops FFl through FF3. The Q output of flip-flop FF 1 iscoupled to the direct reset of the flipflop F F3, the Q output of theflip-flop FF2 is coupled to the direct reset input of the flip-flop FFland the Q output of the flip-flop FF3 is coupled to the direct resetinput of the flip-flop FF 2. As can be seen, the flip-flops FF 1 throughFF3 are coupled in a ring counter configuration. For example, whenflip-flop FF2 is set, the Q output thereof resets flip-flop FFl.

The flip-flops FF4 through FF6 are coupled in identical manner as therespective flip-flops FFl through FF3 with the exception that thesignals X, Y and Z replace the respective signals X, Y and Z.

The Q output of the flip-flop FFI is coupled to the input of a NAND gate200 which functions as an inverter whose output constitutes the triggersignal for the controlled rectifier Al+ in group A+. In like man- 7 ner,the 6 outputs of the flip-flops FF2 through F F6 are coupled torespective NAND gates 202, 204, 206, 208 and 210 whose outputsconstitute the trigger signals for the control rectifiers A2+, A3+, A4+,A5+ and A6+ respectively in group A+.

The flip-flops FF7 to FF12 are enabled when the group signal GP is at alogic 0 by the coupling of the group signal GP to the input of the ANDgate at the reset inputs of the flip-flops FF7 through FF12 and theinverse thereof to one of the inputs of the AND gates at the set inputsthereof. As with flip-flops FFl through FF6, the flip-flops FF7 throughFF12 are set when the remaining input of the AND gate at the set inputsthereof is a logic 1 and the clock input changes from a logic 1 to alogic 0. The inputs to the AND gates at the set and reset inputs of theflip-flops FF7 through FF12 are the inverse of corresponding inputs ofthe flip-flops FFl through FF6 respectively. The clock inputs of theflip-flops FF7 through FF12 are the same as the respective inputs of theflip-flops FFI through FF6. In addition, the flip-flops FF7 through FF9and the flip-flops FF10 through FF12 are coupled in a ring counteconfiguration as the flip-flops FF]. through F F3. The Q outputs of theflip-flops FF7 through FF12 are coupled to respective inputs of NANDgates 212, 214, 216, 218, 220 and 222. The outputs of the NAND gates 212through 222 constitute the trigger signals for the controlled rectifiersAlthrough A6 respectively in group A.

As can be seen in FIG. 3, the flip-flops FFl through FF6 are enabled togenerate trigger signals for the controlled rectifier group A+ duringthe first 180 segment of the group reference signal GP and theflip-flops FF7 through FF12 are enabled to generate trigger signals forthe controlled rectifier group A- during the second 180 segment of thegroup signal GP Further, the flipflops FFl through FF6 are selectivelyenabled by the square wave signals X, Y and Z either directly orinverted to generate trigger signals for the controlled rectifier groupA+as are the flip-flops FF7 through FF12 enabled thereby to generatetrigger signals for the controlled rectifier group A. Each of thetrigger signals are coupled by conventional means such as pulsetransformers to the control electrode of the respective controlledrectifier in groups A+ and A- which are gated conductive thereby.

Except as will hereinafter be described with respect to the inhibitingof the respective trigger signals for controlled rectifiers Al+ throughA6+ and A1 through A6, the controlled rectifiers in groups A+ and A areselectively gated conductive to supply an alternating voltage to thephase winding 30-A as follows with reference to FIGS. 3 and 4. The motorreference signal R is superimposed on each of the source referencesignals R Ry and R in FIG. 4 so as to clearly illustrate, the functionand outputs of the comparators 88, 90 and 92 of FIG. 1. Further, themotor reference signal R is illustrated as a straight line approximationof the digital sawtooth waveforms of FIG. 2 for illustration purposes.

As seen in FIG. 4, the signals V V and V are supplied by the comparators88, 90 and 92 respectively, and become a logic 1 when the motorreference signal R exceeds the magnitude of the source reference signalsR Ry and R respectively. These signals V V and V and particularly theirtrailing edges, represent the trigger signals for the controlledrectifiers in groups A+ and A.

Beginning at time T1 in FIG. 4, the group signal GP is a logic 1 toenable the flip-flops FFl through FF6 and disable the flip-flops FF7through FF12. At time T1, V changes from a logic 1 to a logic 0 whilesquare wavesignal Y is a logic 0 to set flip-flop FFS which resetsflip-flop FF4 through the direct reset input thereof. The output of theNAN D gate 208 shifts from a logic 0 to a logic 1 which constitutes thetrigger signal for the controlled rectifier A5+ which is gated intoconduction. At time T2, the signal V shifts from a logic I to a logic 0while the square wave signal X is a logic 1. Consequently, the flip-flopFFl is set which resets flipflop FF3 to change the trigger signal forthe controlled rectifier A3+, which was previously a logic 1, to a logic0. Upon the setting of flip-flop FF], the output of the NAND gate 200changes from logic 0 to a logic 1 which constitutes the trigger signalfor the controlled rectifier A1+. In the aforementioned manner, theflip-flops FFl through FF6 are periodically set and reset to generatethe trigger signals for the controlled rectifiers A1+ through A6+ ingroup A-lduring the period that the group signal GP is a logic 1 tosupply of the phase A voltage and current signals to the phase winding30-A.

At time T3, the group signal GP changes from a logic 1 to a logic 0 toenable the flip-flops FF7 through FF12 and disable the flip-flops FFlthrough FF6. A short time thereafter, at time T4, the fast fallingtrailing edge of the motor reference signal R occurs. Simultaneouslytherewith, the signals V and V M which were each previously at logic 1change tologic 0. As prior to time T4, flip-flop FFl was set and sincethe inverse of group signal GP is a logic 1 at time T4, the flip-flop PMis reset as the signal V changes from logic 1 to logic 0.to change thetrigger signal for the control rectifier A1+ from logic l to logic 0.Since V remains unchanged at logic 0 through time T3 and T4, theflip-flop FF6 remains set and the trigger signal for controlledrectifier A6+ remains at logic 1 in the new group.

Upon the shifting of the signal V from a logic 1 to a logic 0 at timeT4, the flip-flop FF 7 is set since its two set inputs are at logic 1.Consequently, the output of the NAND gate 212 changes from a logic 0 toa logic 1 to generate a trigger signal for the controlled rectifier A1in group A.

In the circuit previously described, the changing of the signal V y fromlogic 1 to logic 0 at time T4 would set the flip-flop FFll to generate atrigger signal for the controlled rectifier A5 at the output of the NANDgate 220. The fast falling trailing edge of the motor reference signalR, at time T4 results in the switching of the signals V and V from alogic 1 to a logic 0 and therefore the generation of trigger signals atthe output of NAND gates 212 and 220 for controlled rectifiers A1" andA5-. These two trigger signals for Aland A5would have existed had thegroup signal GP been a logic 0 for all times prior to T4 and if motorreferences R had been equal to its value at T4 for all times prior toT4. Therefore, the fast falling trailing edge of the motor reference Rresults in the generation of the proper triggers at time T4 for a smoothtransition of lead current between controlled rectifier groups withouterratic behavior since those controlled rectifiers at the beginning of anew group are triggered that would normally be conducting had this groupalways been conducting. However, if the controlled rectifier A5- wereallowed to conduct for the case illustrated in FIG. 4, a short circuitcondition would result between the controlled rectifiers A5- and A6+since phase voltage y at the output of the winding 12 on conductor 22 ismore positive than phase voltage 2 at the output of the winding 12 onconductor 24 as illustrated in FIGS. 1 and 2. As can be seen, thiscondition exists until time T5 at which time phase voltage 2 becomesmore positive than phase voltage y and the square wave signal Z shiftsfrom a logic to a logic 1 at the output of comparator 74 of FIG. 1.

To prevent the short circuit between the controlled rectifiers A5-andA6+ and further to prevent all possible short circuits which could occurupon thc transition between group A+ and A, inhibiting circuits areprovided in FIG. 3 for inhibiting the trigger signals during the timeperiod that a possible short circuit condition exists.

The O outputs of the flip-flops FFl through FF6 or FF7 through FF12which remain a logic 1 after a state change in the group signal GPindicate which controlled rectifiers were last to be triggered in theprevious group A+ or A. In addition, the square wave signals X, Y and Zprovide an indication of the line-to-line polarity of the voltagesbetween the lines 20, 22, and 24. These signals are combined logicallyto generate inhibit signals for inhibiting those trigger signals whichmay cause short circuits.

As seen in FIG. 3, the inhibit circuits include NAND gates 244 through266 whose outputs are connected respectively to the outputs of the NANDgates 200 to 222. To inhibit the trigger signal for the controlledrectifier A5 and thus prevent the short circuit condition illustrated inFIG. 4, the inverse of the square wave signal Z and the Q output of theflip-flop F F6 are applied to the inputs of the NAND gate 264 tomaintain the trigger signal for the controlled rectifier at logic 0while phase voltage y of phase winding 12 is more positive than phasevoltage 2 during the generation of a trigger signal for the controlledrectifier A6+.

Referring to FIG. 3, at time T4 the inverse of the logic signal Z is alogic 1 and the Q output of flip-flop FF6 is also a logic 1.Consequently, the output of the NAND gate 264 is a logic 0 to inhibitthe generation of the trigger signal for the controlled rectifier A5--until time T5 at which time the inverse of the square wave signal Zshifts to a logic 0 indicating the polarities of the voltages betweenthe conductors 22 and 24 are no longer such as would create a shortcircuit between the control rectifiers A5 and A6+. Therefore, at timeT5, the inhibit signal at the output of the NAND gate 264 is removed topermit the generation of the trigger signal for the controlled rectifierA5-. In like manner, the appropriate signals as indicated in FIG. 3 areapplied to the inputs of the NAND gates 244 through 262 and 266 toprevent all other possible short circuits.

While the group signal GP is a logic 0, the trigger signals for thecontrolled rectifiers Althrough A6 are generated in the same manner asthe trigger signals for the controlled rectifiers Al+through A6+tosupply the second 180 of the phase A current and voltage to the phasewinding -A. As the group A+ and A- each are controlled during respective180 segments of the group signal GP and since the frequency of the groupsignal GP is controlled by the slip frequency controller 62 to thedesired frequency F the frequency of the voltage and current supplied tothe coil 30-A by the groups A+ and A is equal to the desired frequencyFSUIIL" The controlled rectifier groups B+ and B, and C+ and C arecontrolled in the same manner as the controlled rectifiers in groups A+and A- in response to the motor reference signals R R and the groupsignals GP and GP to generate the phase B and C voltages and currentssupplied to the respective phase coils 30-B and 30-C. As the motorreference signals R R and R and the groups signals GP GP H and GP aredisplaced from one another, the phase A, B and C voltages and currentssupplied to the phase coils 30-A, 30-B and 30-C comprise a three-phasealternating voltage and current having a frequency determined by themotoring and braking programmer 62.

Reversal of the induction motor 28 has not been illustrated, it beingobvious to one skilled in the art to provide a motor reverse signal inresponse to operator demand and appropriate logic to reverse thesequence of the phase B and C signals. In general, this is accomplishedby interchanging the group signals GP and GP in the group controlgenerator 66 and by interchanging motor reference signals R B and R Theinterchanging could be done mechanically with relays but preferably itis accomplished electrically with logic gates.

The motor reference generator 68 comprising the sawtooth waveformgenerator of this invention is generally illustrated in FIGS. 5 through7 with reference to the diagrams of FIGS. 8 and 9. Referring to theFigures, a divide by N cour iter 300 having outputs Q through Q has its0, and Q outputs coupled to respective inputs of a NAND gate 302 whoseoutput is inverted by a NAND gate 304 and applied to its data input D soas to function as a divide by 3 counter. The output of the slipfrequency controller 62 of FIG. 1, which is comprised of the voltagepulses having a frequency of 10 is coupled to the clock input of thecounter 300. For purposes of illustration, it will be assumed that theconstant J is equal to 360 so that the voltage pulses supplied to theclock input of the counter 300 has the frequency 360F Therefore the Q1output of the counter 300 is a signal having a frequency IZOFhereinafter referred to as IZOF The inverted form of this signal isillustrated in FIG. 8a. The counter 300 may take the form of the digitalintegrated circuit model CD 4018A manufactured by RCA, Solid StateDivision, Box 3200, Somerville, NJ. 08876.

The l20F l signal is coupled to the clock input of a divide by N counter306 and the clock inputs of a divide by 10 counter 308 and a divide by10 counter 310. The divide by N counter 306 is identical to the divideby N counter 300 and is coupled into a divide by 6 configuration byfeeding back the Q output thereof, hereinafter referred to as 20P (1)3,to the data input thereof. The Q output of the counter 306, hereinafterreferred to as ZOF (b1, and the ZOF (#3 signal are coupled to respectiveinputs of a NAND gate 312 whose output is coupled to the clock enableinput of the counter 308. The clock enable of the counter 310 isgrounded.

The counters 308 and 310 are enabled when the clock enable inputsthereof are grounded. The divide by 10 counter 308 functions in responseto the enabling signal output of the NAND gate 312 and the signal 1201(151 to sequentially supply decoded decimal outputs on 10 output lineswith each output shifting to a logic 1 during a respective decimal timeslot. The output signal on each of the respective lines has a frequencyequal to 21 each being identified respectively by (b1 through (1)10. Inlike manner, the counter 310 functions to divide the 120F,,,,,,, (blsignal by and supplies l0 sequential decoded decimal outputs havingrespective decimal time slots, each output being identified respectivelyas 51 through (1)10 and each having a frequency equal to 12F,,,,,,. Bothcounters 308 and 310 change state on the falling edge of signal lF,',, 1as shown in FIG. 8. The counters 308 and 310 may take the form of thedigital integrated circuit model CD 4017A manufactured by RCA, SolidState Division, Box 3200, Somerville, NJ. 08876.

' To synchronize the operation of the group control generator 66 and themotor reference generator 68, the group signal GP is applied to theinput of a pulse generator 314 which generates a sync pulse S y at eachpositive transition of the GP A signal. The sync pulses Sy are coupledto the reset inputs of the counters 306, 308 and 310 which are resetthereby. The sync pulses S, are redundant-after the first cycle sincethe counters will count end-around on a synchronized basis thereafter.

The 2F,,,,, d 3 signal from the counter 308 is supplied to one input ofa NAND gate 316 of a flip-flop 318. The ZF d 9 signal from the counter308 is supplied to one input of a NAND gate 320 of the flip-flop 318.The 12P (#7 signal from the counter 310 is coupled to a second input ofthe NAND gate 316. The MOTOR/BRAKE signal on conductor 63 from themotoring and braking control circuit 64 of FIG. 1 is coupled to a thirdinput of the NAND gate 316, the second input of the ,NAND gate 320 andto an input of a NAND gate 322 of the flip-flop 318. The output of theNAND gate 316 is coupled to a second input of the NAND gate 322 and theoutput of the NAND gate 320 is coupled to an input of a NAND gate 324 inthe flipflop 318. The outputs of the NAND gates 322 and 324 are crosscoupled to respective inputs thereof to complete the flip-flopconfiguration.

The output of the flip-flop 318 is a digital phase A count-up signal CUAwhich is applied to the data input of the first section of a shiftregister 326 and an input of a NAND gate 328. The shift register 326 iscomprised of four sections of four stages each with the output of thelast stage in each section being coupled to the data input of thefollowing section. The output of the last stage in the shift register326 is coupled to the data input of the first section of an identicalshift register 330, the output of the last stage of which is coupled tothe data input of the first section of a shift register 332 againidentical to the shift register 326.

The 120F 4J1 signal is inverted by a NAND gate 334 and supplied torespective clock inputs of the shift registers 326, 330 and 332. Theoutput of the first section of the shift register 330 comprises adigital phase C count-up signal CUC which is coupled to a respectiveinput of a NAND gate 335 and the output of the second section of theshift register 332 comprises a digital phase B count-up signal CUB whichis coupled to a respective input of a NAND gate 336. The 120F,,,,,,, 1signal at the output of the NAND gate 334 is coupled to respectiveinputs of the NAND gates 328, 335 and 336.

The signal CUA is generated by setting and resetting the flip-flop 318at the appropriate times during each half cycle of motor phase A asshown in FIG. 8. The signals CUB and CUC are generated by delaying CUAby 120 and 60, respectively, with the use of shift registers 326, 330and 332.

Each of the shift registers 326, 330 and 332 may take the form of thedigital integrated circuit model CD 12 4006A manufactured by RCA, SolidState Division, Box 3200, Somerville, NJ. 08876.

When motoring, the MOTOR/BRAKE signal on conductor 63 from the motoringand braking control 68 is a logic 1, and the counters 306, 308 and 310,the flipflop 318, and the shift registers 326, 330 and 332 function togenerate the logic signals CUA, CUB and CUC during the respective groupsignals GP GP 8 and GP phase displaced from one another as illustratedin FIG. 8a. When the signal CUA is at logic 1, the NAND gate 328supplies a series of clock pulses CLK-A at a frequency equal to F,,,,,,.In like manner the NAND gates 335 and 336 function to generaterespective se- 'ries of clock pulses CLK-B and CLK-C during the timeperiod that the CUB and CUC signals are at logic 1..

If the MOTOR/BRAKE signal from the motoring and braking control 68 is alogic 0, indicating braking of the induction motor 28 of FIG. 1, theoutput of the NAND gate 322 of the flip-flop 318 is a constant logic 1.Consequently, the CUA, CUB and CUC signals all shift to and remain at alogic 1 and the CLK-A, CLK-B and CLK-C signals are generated withoutinterruption.

Referring to FIG. 6, the 121 421 signal from counter 310 is inverted bya NAND gate 338 whose output is coupled torespective inputs of NORgates340, 342 and 344. The signals ZF (b1, 21 (#4 and ZF 7 from counter 308are connected to second inputs of NOR gates 340, 342 and 344,respectively. The output of the NOR gates 340, 342 and 344 comprise thepulses PRESET A, PRESET C and PRESET B as illustrated in FIG. 8a, eachoccurring with each state change of the respective group signal GP GPand GP Referring to FIG. 7, a pair of counters 346 and 348 are seriallyconnected and function to count pulses supplied to the clock inputsthereof and supply on respective output lines a 6-bit, binary indicationof the number of pulses counted. These output lines are coupled torespective inputs of an inverter 349. The CLK-A sig-' nal is supplied tothe clock inputs of the counters 346 and 348, the MOTOR/ BRAKE signal iscoupled to selected preset inputs of the counters 346 and 348andthePRESET A signal is coupled to the preset enable inputs of thecounters 346 and 348. A positive voltage Vrlfrom a suitable power supplyis coupled to the counters 346 and 348.

During motoring, the MOTOR/BRAKE signal is a logic 1 and upon theoccurrence of the PRESET A signal, the counters 346 and 348 are set to apreselected number designated at the .11, 12,13 and .14 jam inputs. Whenthe CUA signal changes to logic 1, the CLK-A pulses are supplied to theclock inputs of the counters 346 and 348 which in turn generate a binaryindication on the output lines thereof representing the sum of thenumber of pulses supplied thereto and the preset number. The inverter349 functions to invert the respective outputs of the counters 346 and348 and supplies the inverted signals to a digital-to-analogconverter350. Each of the counters 346 and 348 may take the form of the digitalintegrated circuit model CD 4029A manufactured by RCA, Solid StateDivision, Box 3200, Somerville, NJ. 08876. 7

Assuming a maximum count of 63 by the counters 346 and 348, the outputof the digital-to-analog converter 350 is a current defined by theexpression I I r: K1 N where K is a constant, V is the magnitude of thegain control voltage coupled to the digital-to-analog converter 350through the resistor 352 from the conductor 65 and N is the numberstored in the counters 346 and 348. This output is coupled to thenegative input of an operational amplifier 354 having a feedbackresistor 355 with a resistance R As the counter 346 and 348 count theinput pulses supplied thereto, the output of the digital-to-analogconverter 350 is a negative increasing stepped current waveform having amagnitude represented by equation (I) which is converted to a positiveincreasing stepped voltage R, by the amplifier 354. The magnitude ofeach of the stepped increments and consequently the magnitude of thecurrent I and voltage R, can be directly controlled by varying themagnitude V of the gain control voltage applied to the gain ad jastmentresistor 352. The digital-to-analog converter 350 may take the form ofmodel MC 1406L manufactured by Motorola, Box 20912, Phoenix, Ariz.85036.

The gain control voltage having the magnitude V represents a specificbraking or motor command on the conductor 65 from the motoring andbraking control 64 is coupled to the digital-to-analog converter 350.This gain control voltage is effective for controlling the gain of thedigital-to-analog converter 350.

The gain control signal on conductor 65 is further coupled to groundacross a potentiometer 364 whose wiper arm is coupled to a bufferamplifier 366 having unit gain. The output of the amplifier 366 iscoupled to the negative input of the operational amplifier 354 through aresistor 368 having a resistance R The current input to the operationamplifier 354 from the amplifier 366 is defined by the expression I2=(K2r;)/ 2 a V1. where K is a constant determined by the setting of thepotentiometer 364, R is the resistance of the resistor 368, K K /R and Vis the magnitude of the gain control voltage. I

A potentiometer 370 is coupled between the source of negative voltage Vand ground and supplies a negative current to the negative input of theoperational amplifier 354 through a resistor 371 having a resistance RThe current supplied to the operational amplifier 354 from thepotentiometer 370 is defined by the expression the expression RA r 12 1) =VG(RFKIN RI-'K.1)+RFK5 (4) For a given setting of thepotentiometer 364 establishing a particular valve of K the expressionwithin the brackets of equation (4) goes to zero for a specific countoutput of the counters 346 and 348 for all values of V This point willhereinafter be referred to as the zero gain point for the motorreference signal R At that count, the motor reference signal R A isequal to the expression R K of equation (4), the magnitude of which iscontrolled by adjusting the magnitude of I\',-, with the potentiometer370. As can be seen from equation (4), the expression R K functions toestablish a 14 bias for the curve established by the expression V ,-(R KK3).

The generation of the motor reference signal R,, will now be describedwith reference to FIGS. 7 and 8. Assuming the MOTOR/BRAKE signal is alogic 1 representing motoring, upon the occurrence of the signal PRESETA, the counters 346 and 348 are preset to a preselected value which maybe, for example, 11. The counters 346 and 348 remain in this state untilthe count-up signal CUA shifts to a logic 1 to enable the NAND gate 328of FIG. 5 to supply the signal CLK-A at the frequency 12OF to clock thecounters 346 and 348. Thereafter, the output of the counters 346 and 348is a binary representation of the number of pulses supplied thereto-plusthe initial preset value. With each pulse counted by the counters 346and 348, the digitalto-analog converter 350 increases the magnitude ofthe signal supplied to the operational amplifier 354 by a valuedetermined by the magnitude V of the gain control. As seen in FIG. 8a,it is assumed that the magnitude V of the gain control voltage, theoutputs of the voltage dividers 364 and 370 are such that with the countof 11 preset into the counters 346 and 348, the output of theoperational amplifier 354 is equal to 0.25 volts. The output currentfrom the digital-to-analog converter 350 continues to increase instepwise manner in accordance with each count of the counter 346 and 348and the magnitude V of the gain control voltage until the CUA signalshifts to logic 0 to inhibit the NAND gate 328 from generating the CLK-Apulses. As seen in FIG. 8a, the magnitude of the output of theoperational amplifier 354 in the specific example is at this time equalto 4.25 volts. Upon the occurrence of the next pulse PRESET A, thecounters 346 and 348 are preset and the cycle is repeated. The resultingwaveform is the desired truncated sawtooth waveform for controlling thefiring angle delay of the control switches in the groups A+ and A duringmotoring.

To provide for braking, the vehicle operator causes the motoring andbraking control 68 to supply a logic 0 to the preset inputs of thecounters 346 and 348 and also to cause the signals CUA, CUB and CUC tobe maintained ata logic I as previously described so as to continuallymaintain the NAND gates 328, 334 and 336 enabled to supply therespective output clock pulses CLK-A, CLK-B and CLK-C. .Consequently,upon the occurrence of the pulse PRESET A, the counters 346 and 348 arereset to 0 and, after the pulse PRESET A changes to a logic 0, thecounters 346 and 348 begin to count the CLK-A pulses. Also upongenerating the logic 0 MOTOR/BRAKE signal, the vehicle operator causesthe motoring and braking control 68 to decrease the magnitude V of thegain control voltage to reduce the gain of the digital-to-analogconverter 350 to effect the decrease of the magnitude of eachincremental step of the output waveform thereof. The output of theoperation al amplifier 354 continues to increase in stepwise fashionuntil the next pulse PRESET A at which time the counters 346 and 348 areagain set to 0 after which the cycle is then repeated. The resultingsignal is the conventional sawtooth waveform illus trated in FIG. 8bvarying in amplitude from 1.0 volts to 4.0 volts. Due to the time delaythrough the various circuit elements, the trailing edge of the motorreference signal R occurs after the state change of the group signal GPReferring to FIGS. 9a and 9b, one of the significant features of themotor reference generator 68 will be described. For a given setting ofthe potentiometer 364, the zero gain point for the motor referencesignal R is established about which the motor reference signal R can becompressed or expanded by varying the gain control voltage V In FIG. 9a,the sawtooth waveform 372 is shown for one specific magnitude V of thegain control voltage and the curve 374 is a sawtooth waveform shown witha decreased magnitude V of the gain control voltage. As can be seen bythe FIG. 9a, the point of intersection of the curves 372 and 374 atpoint 376 is established by the potentiometer 364 and remains constantfor all values of V In this manner, the range of trigger delay angles ofthe controlled switches in groups A+ and A can be varied so as tocontrol the amplitude of the phase A signal to the induction motorwinding 30-A. Although FIG. 9a illustrates the motor reference signal Rduring braking, it is applicable also to the truncated sawtooth waveformgenerated for motoring. Further, the curves may be biased upward ordownward by varying the setting of potentiometer 370.

FIG.'9b illustrates the motor reference signal R,, for a second settingof the potentiometer 364 with two magnitudes of gain control voltage.The sawtooth waveform 378 is established by a first magnitude V of thegain control voltage and the sawtooth waveform 380 is established by asecond magnitude of the gain control voltage. As can be seen, the pointof intersection 382 of the sawtooth waveforms 378 and 380 is shifted asa function of the potentiometer 364 and remains constant for thatsetting. In the foregoing manner, the zero gain point for the motorreference signal R, can be established about which it may be compressedor expanded. Further, by varying the potentiometer 370, the sawtoothwaveforms 37 2 through 380 can be biased up or down without altering therelative intersection points 376 and 382.

The motor reference signals R and R are generated by the R and Rreference generators 384 and 386 in identical manner as the motorreference signal R in response to the pulses PRESET B and PRESET C andthe clock signals CLK-B and CLK-C which establish the desired phaserelationships between the motor reference signals R R and R Due to theabsence of timing elements in the motor reference generator 68, thegenerator is not frequency dependent and can operate to generate truesawtooth waveforms at all speeds of the induction motor 28 down to zerospeed. Further, since the gain control voltage is applied to all threereference generators R R and R the amplitudes of all three referencesignals are controlled simultaneously. The nature of this circuit issuch that R R B and R can be identical in shape and amplitude, can beexactly 120 apart, can be controlled together as one with respect toshape and amplitude, and can have very low drift since amplitudes aredetermined by digital signals and only a few resistor ratios.

The detailed description of the preferred embodiment of this inventionfor the purpose of explaining the principles thereof is not to beconsidered as limiting or restricting the invention, since manymodifications may be made by the exercise of skill in the art withoutdeparting from the scope of the invention.

What is claimed is:

1. A digital sawtooth waveform generator comprising: means forgenerating a series of clock pulses; means for generating a series ofrecurring preset pulses; counting means for receiving said series ofclock pulses and recurring preset pulses and counting said clock pulsesbetween preset pulses to provide a digital signal representing thenumber of clock pulses counted thereby between preset pulses; means forgenerating a gain control signal having a magnitude V a variable gaindigital-to-analog converter for receiving the digital signal and thegain control signal and supplying a first signal having a magnitudeequal to the product of V N and a first constant where N is the countrepresented by the digital signal; means for generating a second signalhaving a magnitude equal to the product of V and a second constant, thesecond signal having a polarity opposite to the polarity of the firstsignal; and means for summing the first and second signals, whereby thesummation is a digital sawtooth waveform which is compressed or expandedabout a particular count N equal to the second constant divided by thefirst constant as the magnitude V of the gain control signal is varied.

2. A digital sawtooth waveform generator comprising: means forgenerating a series of clock pulses having a frequency defined by theexpression JF where J is a constant and F is a desired frequency of thesawtooth waveforms; means for generating a series of preset pulses atthe frequency F; a digital counter for receiving the preset and clockpulses and generating a digital number representing a totalized count,the totalized count being equal to the sum of a preset number and thenumber of clock pulses received by the digital counter following apreset pulse; means for generating a gain control signal having amagnitude V a variable gain digital-to-analog converter for receivingthe digital signal and the gain control signal and supplying a firstoutput signal having a magnitude equal to the product of V N and a firstconstant where N is the magnitude of the totalized count; means forgenerating a second output signal having a magnitude equal to theproduct of V and a second constant, the second output signal having apolarity opposite to the polarity of the first output signal; and meansfor summing the first and second output signals, whereby the summationis a digital sawtooth waveform which is compressed or expanded about apreselected totalized count N equal to the second constant divided bythe first constant as the magnitude V of the gain control signal isvaried.

3. A digital sawtooth waveform generator comprising: means forgenerating a series of clock pulses having a frequency defined by theexpression JF where J is a constant and F is a desired frequency of thesawtooth waveforms; means for generating a series of preset pulses atthe frequency F; a digital counter for receiving the preset and clockpulses and generating a digital number representing a totalized count,the totalized count being equal to the sum of a preset number and thenumber of clock pulses received by the digital counter following apreset pulse; means for generating a gain control signal having amagnitude V a variable gain digital-to-analog converter for receivingthe digital signal and the gain control signal and supplying a firstsignal having a magnitude equal to the product of V N and a firstconstant where N is the magnitude of the totalized count; means forgenerating a second signal having a magnitude equal to the product of Vand a I second constant, the second signal having a polarity op- 3 ,924, l 9 17 18 about a preselected totalized count N equal to thesecconstant when the totalized count is equal to the preseond constantdivided by the first constant as the magnilected totalized count for allvalues of the magnitude tude V of the gain control signal is varied andwhereby V the amplitude of the summation is equal to the third 5

1. A digital sawtooth waveform generator comprising: means forgenerating a series of clock pulses; means for generating a series ofrecurring preset pulses; counting means for receiving said series ofclock pulses and recurring preset pulses and counting said clock pulsesbetween preset pulses to provide a digitaL signal representing thenumber of clock pulses counted thereby between preset pulses; means forgenerating a gain control signal having a magnitude VG; a variable gaindigital-toanalog converter for receiving the digital signal and the gaincontrol signal and supplying a first signal having a magnitude equal tothe product of VG, N and a first constant where N is the countrepresented by the digital signal; means for generating a second signalhaving a magnitude equal to the product of VG and a second constant, thesecond signal having a polarity opposite to the polarity of the firstsignal; and means for summing the first and second signals, whereby thesummation is a digital sawtooth waveform which is compressed or expandedabout a particular count N equal to the second constant divided by thefirst constant as the magnitude VG of the gain control signal is varied.2. A digital sawtooth waveform generator comprising: means forgenerating a series of clock pulses having a frequency defined by theexpression JF where J is a constant and F is a desired frequency of thesawtooth waveforms; means for generating a series of preset pulses atthe frequency F; a digital counter for receiving the preset and clockpulses and generating a digital number representing a totalized count,the totalized count being equal to the sum of a preset number and thenumber of clock pulses received by the digital counter following apreset pulse; means for generating a gain control signal having amagnitude VG; a variable gain digital-to-analog converter for receivingthe digital signal and the gain control signal and supplying a firstoutput signal having a magnitude equal to the product of VG, N and afirst constant where N is the magnitude of the totalized count; meansfor generating a second output signal having a magnitude equal to theproduct of VG and a second constant, the second output signal having apolarity opposite to the polarity of the first output signal; and meansfor summing the first and second output signals, whereby the summationis a digital sawtooth waveform which is compressed or expanded about apreselected totalized count N equal to the second constant divided bythe first constant as the magnitude VG of the gain control signal isvaried.
 3. A digital sawtooth waveform generator comprising: means forgenerating a series of clock pulses having a frequency defined by theexpression JF where J is a constant and F is a desired frequency of thesawtooth waveforms; means for generating a series of preset pulses atthe frequency F; a digital counter for receiving the preset and clockpulses and generating a digital number representing a totalized count,the totalized count being equal to the sum of a preset number and thenumber of clock pulses received by the digital counter following apreset pulse; means for generating a gain control signal having amagnitude VG; a variable gain digital-to-analog converter for receivingthe digital signal and the gain control signal and supplying a firstsignal having a magnitude equal to the product of VG, N and a firstconstant where N is the magnitude of the totalized count; means forgenerating a second signal having a magnitude equal to the product of VGand a second constant, the second signal having a polarity opposite tothe polarity of the first signal; means for generating a third signalhaving a magnitude equal to a third constant; and means for summing thefirst, second and third signals, whereby the summation is a digitalsawtooth waveform which is compressed or expanded about a preselectedtotalized count N equal to the second constant divided by the firstconstant as the magnitude VG of the gain control signal is varied andwhereby the amplitude of the summation is equal to the third constantwhen the totalized count is equal to the preselected totalized count forall values of the magnitude VG.